Deliverables
The objective for the first six months of the Mont-Blanc Project can be summarized as to have a fully functional framework in all work packages. This objective involves setting up the necessary technical infrastructure and adequate methodology in each of the work packages.
This document defines the dissemination objectives for the Mont-Blanc project, as well as the different targets for all its activities, the dissemination tools, the interaction with similar projects, its activities to be done during the Mont-Blanc project, and the policy used to disseminate the results. The aim of this document is to define the strategy for disseminating the project results taking into account the big social impact that this project will have on society. This plan intends to raise awareness and interest in the developed technologies and solutions among the target groups such as the users, the scientific community, the IT industry and the general public. The strong presence of leading research HPC institutions ensures the wider dissemination potential through scientific channels, and the industrial partners will focus more on the exploitation and technology transfer activities. Most of the results will be published via academic and industrial channels by submitting scientific papers, and by holding workshops, courses and tutorials related to the new technologies.
The objective of the Initial Press Release Deliverable is to 1) define a general strategy for creating and publishing press releases as well as to 2) report on the outcome of the initial and follow-up press releases for the Mont-Blanc Project. This press release must be sent out by all partners to all press contacts locally as well as translated to local languages, if needed. As stated in the Dissemination Strategy Document (D 2.1), there will be a planning for future press releases during the project. The press release strategy defined should be consistent with the dissemination strategy and its objectives and will be maintained throughout the Mont-Blanc project.
This document describes the structure, content and updates process of the Mont-Blanc public web site (www.montblanc-project.eu). Web presence is a central element in the dissemination activities of Mont-Blanc, as indicated in the Dissemination Strategy Document (D 2.1). The website became publically available in October 2011. The Barcelona Supercomputing Center, as coordinator of the project, hosts and maintains the website. This document describes how the website was created and how it will be maintained. It also describes the structure of the website and the functions that are available to the user.
The following document reports on the selection of the performance-critical kernels to be ported to the OmpSs [5] programming model during the course of the project. This work, started within WP3-T3.1 and now continuing in WP3-T3.2 and WP3-T3.3, pursues on the one hand an increased performance and portability of the kernels themselves due to the shift of paradigm from a serial or thread-oriented model to a task-based model supported by an ecient run-time scheduler. On the other hand it should devise a set of best-practices to provide WP4 colleagues with helpful guidelines when porting full applications.
The Mont Blanc project aims to assess the potential of low power embedded components based clusters to address future Exascale HPC needs. The role of work package 4 (WP4, “Exascale applications”) is to port, co design and optimise up to 11 real exascale-class scientific applications to the different generation of platforms available in order to assess the global programmability and the performance of such systems. The first section will introduce the different applications and their different characteristics, the second section will describe the platforms used by WP4 during the first year, the third section will report the progress of the porting and the profiling of each of the 11 applications during the first year and the last section will give perspectives on WP4 activities.
This report summarizes the dissemination activities carried out by the Mont-Blanc project in the October 2011– October 2012 period. Specifically, in the following pages a complete list of conferences as well as the presentations made at various events and workshops and related to the project will be listed. Furthermore, any additional coverage of the project by the press and online media is also presented in this document. During this first year of Mont-Blanc, the consortium published a total of one technical report, and attended to 49 conferences, workshops or seminars. Moreover, the consortium organized two successful trainings, where other EU funded projects were invited attendees. The high media impact of the project has raised high expectation among the HPC community. For this reason, the overall dissemination output of Mont-Blanc is an indication of the European excellence and recognition of the project partners.
In this Mont-Blanc deliverable we present the current status of porting to the ARM architecture of the OmpSs (Mercurium compiler and Nanos++ runtime system), the Extrae instrumentation library and the Scalasca instrumentation facilities. In addition, we present an initial evaluation of the overhead observed in the OmpSs programming model when using Extrae instrumentation in the Intel architecture.
Nowadays, topmost high performance computing (HPC) clusters use scalable distributed parallel le systems that are able to stripe data over multiple servers to achieve high performance also in I/O. From our experience in the Storage Systems Research Group and given the requirements of the project, we chose a parallel le system that is very common, open-source and POSIX compliant: Lustre; as the rst candidate to provide high performance I/O on our ARM cluster. Given that Lustre is open source we are able to access its code and adapt it to our Linux kernel (provided by SECO) for the ARM architecture. In the meantime, we focused on the client part since the server part is not expected to be executed in the ARM cluster. Thus, we started spending our e orts on adapting the code of the Lustre client modules to our speci c kernel version. As expected, we got some important compilation errors due to kernel incompatibilities, since last maintenance release of Lustre is compatible with kernel versions up to 2.6.32 whereas our current version is 2.6.36 (based on an Ubuntu Maverick distribution). However, we lately got a rst patched version of the Lustre client that can do mostly all of the most common and important POSIX operations. The problem is that due to circumstances we still do not control, when executing some speci c deletion operations causes the client to hang. From this deliverable on we will more e orts to try to understand what is really happening, whether it is an issue related with the architecture or the changes we performed that still need to be further reviewed.
The Mont-Blanc project will produce the rst large-scale supercomputer based on ARM cores. The ARM architecture has been succesfully used in the past in embedded and mobile platforms. However, the requirements and constrains of those platforms greatly di er from the needs of a High Performance Computing (HPC) system. One of these major di erences is the system software used in each environment. Embedded and mobile computing programmers typically use Operating Systems and li- braries customized for their target application (e.g., Android). Moreover, such platforms typi- cally target applications that run in a single MPSoC chip. This is in contrast to a typicall HPC environment, where general purpose operating systems (e.g., Linux) and scientic libraries (e.g., BLAS) are used to run applications in hundreds or thousands of compute nodes in parallel. This document describes initial work done to create a functional HPC system based on ARM cores, from the operating system, to the scienti c libraries, and parallel execution. Such work does not only involve the port of system software to the ARM architecbure, but also tuning these software components to fully exploit the characteristics of ARM cores. Similarly, the cluster management system also needs to be adapted to the characteristics of ARM-based nodes and to the goal of achieving very high energy eciency.
Energy-ecient high performance computing extends beyond the use of energy-ecient low power processing hardware. With increasing variations in the power consumption depending on the workload of a high performance computing system, modern supercomputers need tighter integration with their surrounding data center infrastructure than ever before, causing new challenges for the design and operation of data centers and systems.
Main aspects covered in this document are the power supply chain and the cooling system of the data center and the supercomputer. Regarding the powering of the data center, the main goal for energy ecient operation is to avoid unnecessary conversion steps as they are inherently causing electrical losses, thus reducing overall energy eciency. Also, the use of uninterruptible power supplies should be avoided if availability is only a minor concern like in most typical high
performance computing systems. In the system itself, power saving features such as voltage and frequency scaling and power gating should be used to tune the system hardware according to the scienti c workload's needs.
With respect to cooling, water instead of air is becoming a increasingly accepted cooling medium for data centers. However, in a prototype like the Mont-Blanc system using air cooling can still be a viable option if its drawbacks are mitigated by using rear door heat exchangers in the racks.
Finally, optimized operation despite the increase in complexity of modern high performance systems and data centers can only be achieved by thorough and integrated monitoring of all parameters in the power supply chain, the cooling system and the IT system. In particular, per-node power monitoring should be implemented in order to enable energy based accounting on a per-job basis.
