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Project history

Compute efficiency and energy efficiency are more than ever major concerns for future Exascale systems. Since October 2011, the aim of the European projects called Mont-Blanc has been to design a new type of computer architecture capable of setting future global HPC standards, built from energy efficient Arm solutions.

Phases 1 (2011-2015) and 2 (2013-2016) of the project were coordinated by the Barcelona Supercomputing Center (BSC). They investigated the usage of low-power Arm processors for HPC and gave rise to the world’s first Arm-based HPC cluster, which  helped demonstrate the viability of using Arm technology for HPC.

The third phase of the Mont-Blanc project started in October 2015: it is coordinated by Bull (Atos group). It aims at designing a new high-end HPC platform that is able to deliver a new level of performance / energy ratio when executing real applications.

Finally, Mont-Blanc 2020 is a spin-off of the previous projects. It is coordinated by Bull (Atos group) and started in December 2017. It ambitions to trigger the development of the next generation of industrial processor for Big Data and High Performance Computing.

Four successive projects funded by the European Commission, a common aim: European, energy-efficient HPC

Mont-Blanc 1 (2011-2015)

The first phase of Mont-Blanc was coordinated by the Barcelona Supercomputing Center (BSC) and had a budget of over 14 million, including over 8 million Euros funded by the European Commission.

From 2011 – 2015, the Mont-Blanc project had the following three objectives:

  • To develop a full energy-efficient HPC prototype using low-power commercially available embedded technology.
  • To design a next-generation HPC system together with a range of embedded tchnologies in order to overcome the limitations identified in the prototype system.
  • To develop a portfolio of exascale applications to be run on this new generation of HPC systems.

Its ambition was to imagine a new type of computer architecture capable of setting future global HPC standards that will provide Exascale performance using 15 to 30 times less energy.

Mont-Blanc 2 (2013-2016)

Phase 2 of the project was again coordinated by the Barcelona Supercomputing Center (BSC). Two years after the start of the initial project, the European Commission granted an additional 8 million Euro to extend the Mont-Blanc project activities until September 2016. This three-year extension enabled further development of the OmpSs parallel programming model to automatically exploit multiple cluster nodes, transparent application check pointing for fault tolerance, support for ARMv8 64-bit processors, and the initial design of the Mont-Blanc Exascale architecture.

This phase had the following three objectives:

  • To complement the effort on the Mont-Blanc system software stack, with emphasis on programmer tools (debugger, performance analysis), system resiliency (from applications to architecture support), and ARM 64-bit support
  • To produce a first definition of the Mont-Blanc Exascale architecture, exploring different alternatives for the compute node (from low-power mobile sockets to special-purpose high-end ARM chips), and its implications on the rest of the system
  • To track the evolution of ARM-based systems, deploying small cluster systems to test new processors that were not available for the original Mont-Blanc prototype (both mobile processors and ARM server chips)
  • To provide continued support for the Mont-Blanc consortium, namely operations of the Mont-Blanc prototype, and hands-on support for the application developers

This extension of Mont-Blanc contributed to the development of extreme scale energy-efficient platforms, with potential for Exascale computing, addressing the challenges of massive parallelism, heterogeneous computing, and resiliency.

Mont-Blanc 3 (2015-2018)

The third phase of the Mont-Blanc project started in October 2015: it is coordinated by Bull (Atos group), and has a budget of 7.9 million Euros, funded by the European Commission under the Horizon 2020 programme. The third phase adopts a co-design approach to ensure that hardware and system innovations are readily translated into benefits for HPC applications. It aims at designing a new high-end HPC platform that is able to deliver a new level of performance / energy ratio when executing real applications.

The third phase of the Mont-Blanc project builds upon the previous FP7 projects, with Arm, BSC & Bull being involved in all three projects. It adopts a co-design approach to ensure that hardware and system innovations are readily translated into benefits for HPC applications. It aims at designing a new high-end HPC platform that is able to deliver a new level of performance / energy ratio when executing real applications. This encompasses the three following objectives:

  • To design a well-balanced architecture and to deliver the design for an ARM based SoC (System-on-a-Chip) or SoP (System-on-Package) capable of providing pre-exascale performance when implemented in the 2019-2020time frame. The predicted performance target must be measured using real HPC applications.
  • To maximise the benefit for HPC applications with new high-performance Arm processors and throughput-oriented compute accelerators designed to work together.
  • To develop the necessary software ecosystem for the future SoC. This additional objective is key to ensure that the project successfully translates into an industrial offer for the HPC market.

Mont-Blanc 2020 (2017-2020)

Following on from the three successive Mont-Blanc projects since 2011, the three core partners Arm, Barcelona Supercomputing Center and Bull (Atos Group) have united again to trigger the development of the next generation of industrial processor for Big Data and High Performance Computing. The Mont-Blanc 2020 consortium also includes CEA, Forschungszentrum Jülich, Kalray, and SemiDynamics.

The Mont-Blanc 2020 project has a budget of 10.1 million Euros, funded by the European Commission under the Horizon2020 program. It was launched in December 2017.

It intends to pave the way to the future low-power European processor for Exascale. To improve the economic sustainability of the processor generations that will result from the Mont-Blanc 2020 effort, the project includes the analysis of the requirements of other markets. The project’s strategy based on modular packaging would make it possible to create a family of SoCs targeting different markets, such as “embedded HPC” for autonomous driving. The project’s actual objectives are to:

  • define a low-power System-on-Chip architecture targeting Exascale;
  • implement new critical building blocks (IPs) and provide a blueprint for its first generation implementation;
  • deliver initial proof-of-concept demonstration of its critical components on real life applications;
  • explore the reuse of the building blocks to serve other markets than HPC, with methodologies enabling a better time-predictability, especially for mixed-critical applications where guaranteed execution & response times are crucial.

Project data